Search - vhdl encoder

[Embeded-SCM Develop] 卷积码、CRC

Description: 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6873 | Author: 潘华林 | Hits:

[EditBox] enc

Description: HDB3编码器使用VHDL编制对于基带传输很有用的程序-HDB3 encoder using VHDL preparation for baseband transmission useful procedure
Platform: | Size: 1135 | Author: ls | Hits:

[Com Port] bianmaqishixian

Description: 这是一个编码器的实现的程序，用VHDL语言实现-This is an encoder on the realization of the program, VHDL
Platform: | Size: 66735 | Author: 李芹 | Hits:

[Other resource] VHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642650 | Author: Jawen | Hits:

[Other resource] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3152400 | Author: Jawen | Hits:

[Other resource] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10174 | Author: 孟轲敏 | Hits:

[Other resource] VHDLexample49

Description: VHDL的49个例子，例子丰富，有计数器、状态机、寄存器、汉明纠错码编码器、游戏程序-VHDL 49 examples, examples of rich, counters, state machines, register, Hamming ECC encoder, Games, etc.
Platform: | Size: 44507 | Author: 刘一 | Hits:

[Other resource] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 77351 | Author: 王文 | Hits:

[Other resource] decdor_38

Description: 用VHDL编的编码器,具有多种功能,希望呢温暖感跟大家共享~!-VHDL addendum to the encoder, with a variety of functions and warm sense of hope do share with you ~!
Platform: | Size: 1310 | Author: leochen | Hits:

[Other resource] sdgshjd

Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar] - 4 division of vhdl source [vh dl example. rar] - highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
Platform: | Size: 838 | Author: 张瑞 | Hits:

[Other resource] 8b_10b

Description: vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: | Size: 73116 | Author: 聂样 | Hits:

[Other] mp3_decoder

Description: mp3的VHDL实现，包括HUFFMAN编码器，量化器，子带滤波器．可用来开发：ＦＰＧＡ，ＡＳＩＣ．-mp3 of VHDL, including HUFFMAN encoder, quantizer, subband filters. Can be used to develop : FPGA, ASIC.
Platform: | Size: 37673 | Author: 六六 | Hits:

[Com Port] bianmaqishixian

Description: 这是一个编码器的实现的程序，用VHDL语言实现-This is an encoder on the realization of the program, VHDL
Platform: | Size: 66560 | Author: 李芹 | Hits:

[Other] 3GPPjiaozhi

Description: 3Gpp 25.212 交织器交织深度1024进行行内行间交织-3Gpp 25.212 intertwined depth interleaver 1,024 firms conducted between experts intertwined
Platform: | Size: 2048 | Author: 李春晖 | Hits:

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[Embeded-SCM Develop] 卷积码、CRC

[EditBox] enc

[Com Port] bianmaqishixian

[Other resource] VHDL_Development_Board_Sources

[Other resource] Verilog_Development_Board_Sources

[Other resource] AEScoremodules

[Other resource] VHDLexample49

[Other resource] RS(32to28)encoderanddecoder

[Other resource] decdor_38

[Other resource] sdgshjd

[Other resource] 8b_10b

[Other] mp3_decoder

[Com Port] bianmaqishixian

[Other] 3GPPjiaozhi

[Compress-Decompress algrithms] 601792346200732319490634862

[VHDL-FPGA-Verilog] decdor_38

[VHDL-FPGA-Verilog] DCT

[VHDL-FPGA-Verilog] fifo8_8

[VHDL-FPGA-Verilog] Dualpriorityencoder

[VHDL-FPGA-Verilog] decoder_2_10

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